1. Technical Field
This disclosure pertains to computing systems, and in particular (but not exclusively) to communications of a network-on-chip.
2. Background Art
As integration densities continue to increase in power limited computing environments, multi-core processors provide increased performance vs. power efficiency through parallel processing at reduced voltages and frequencies. Interconnect networks, such as those for on-die communication between cores, are key to enabling scalable performance as the number of cores increases. Circuit-switched networks offer a dedicated channel during data transmission without the need for intermediate buffering or arbitration. This can offer lower power consumption—at least by allowing a reduction of data storage clock power—and higher throughput, as compared with packet-switched networks. Consequently, packet-switched networks can achieve higher resource utilization especially for smaller bit-width messages.
However, by avoiding buffering and arbitration, the dedicated channel resources must be reserved prior to data transmission, possibly preventing other more optimal data transmissions from occurring. Unlike pre-scheduled source-directed routing schemes, distributed routing schemes are not limited to predefined traffic patterns or applications, but determine packet routes and priorities for the reservation of resources based on incomplete real-time information.
Furthermore, network topologies such as mesh and hierarchical tree (also referred to as hierarchical star) offer different trade-offs in overall power vs. bandwidth. A mesh network favors a uniform traffic distribution with more gradual performance penalties as distances increase. A hierarchical star topology provides for relatively improved performance for more local traffic by reducing the overall router hop count. The varying requirements of future integrated network-on-chip (NoC) applications suggest a heterogeneous approach, with multiple on-die networks of different topologies and efficiency tradeoffs.